Bank structure storage control device and paper matter authentication device

ABSTRACT

A storage control device of bank structure is provided which comprises a CPU  1  and a storage  2  connected to CPU  1 . Storage  2  detects and temporarily holds one of the bank addresses 0DF00h-7DF07h of the bank memories  9  to be read out next by CPU  1  when one of the bank memories  9  is read out by CPU  1  so that storage  2  supplies the held bank address 0DF00h-7DF07h to a memory control device  3  which thereby is switched to a next bank memory when CPU  1  produces a next retrieval signal. Accordingly, CPU  1  of small capacity reads information from storage of larger capacity to operate a controlled system connected to CPU  1  of the storage control device.

TECHNICAL FIELD

[0001] The present invention relates to a storage control device of bankstructure in particular of the type capable of operating a controlledsystem connected to and by a small capacity central processing unit inaccordance with information retrieved from a large capacity storage tothe central processing unit, more specifically a storage control deviceof bank structure and an apparatus for validating valuable papers with acentral processing unit connected to a small capacity memoryexchangeable for a large capacity storage for alteration or expansion ofcontrol program.

BACKGROUND OF THE INVENTION

[0002] Lots of current industrial fields have been utilizing electronicmemory devices for storing information and central processing units(CPUs) for reading information from the memory devices to processnecessary functions. For example, FIGS. 3 to 5 illustrate an apparatusthat comprises a memory and a CPU to discriminate or validate valuablepapers such as bills or coupons.

[0003] As shown in FIG. 3, an apparatus 10 for validating valuablepapers comprises a magnetic sensor 22 of magnetic head or Hall effectelement disposed adjacent to a passageway 29, optical sensors 23 to 26of photocouplers each consisting of a light emitting diode and a lightreceiving transistor. Magnetic sensor 22 and optical sensors 23 to 26provide a validating sensor 21 deployed in the proximity of passageway29 so that a central processing unit or CPU 1 validates authenticity ofa valuable paper and produces drive signals to a conveyor 16 in view ofoutputs from validating sensor 21.

[0004] Passageway 29 is defined by conveyor 16 which comprises conveybelts 15 wound around drive pulleys 17 and guide walls 15 a mounted inparallel relation to convey belts 15. Magnetic sensor 22 detects ferrousink printed in a predetermined position on valuable paper. An opticalsensor 23 located adjacent to an inlet 14 detects insertion of valuablepaper into inlet 14 and an optical pattern of infrared ray penetratingthe paper. For instance, optical sensor 23 comprises a light emittingdiode 23 a secured to lower frame 30 of validating apparatus 10 and alight receiving transistor 23 b secured on upper frame 31.

[0005] Upper frame 31 is rotatably connected to lower frame 30 through ahinged structure not shown to upwardly open an end of upper frame 31away from lower frame 30 to remove a jammed paper in passageway 29.Lower and upper frames 30, 31 form an entire frame of validatingapparatus 10. Each of optical sensors 24, 25 comprises a light emittingdiode and a light receiving transistor and a case for accommodatingthese light emitting and receiving elements to receive lights reflectedon upper and bottom surfaces of the paper by each light receivingtransistor. Optical sensor 26 comprises a light emitting diode 26 asecured to lower frame 30 and a light receiving transistor 26 b securedto upper frame 31 to detect permeation pattern of infrared raypenetrating the paper and thereby to sense passage and moved position ofthe paper.

[0006] A pinch roller 27 pushes the paper on magnetic sensor 22 topositively detect magnetic signals from the paper by magnetic sensor 22.Rotatably mounted on lower frame 30 are drive pulleys 17 around whichconvey belts 15 are wound, and rollers 32, 33 are rotatably attached toupper frame 31 opposite to drive pulleys 17 to push the paper on conveybelts 15 by rollers 32, 33. Also, rotatably mounted around a shaft 35behind optical sensor 25 is a lever 34 for detecting passage of paper,and to this end, one end of lever 34 is so resiliently drawn by a spring36 that the other end of lever 34 projects into passageway 29. Passinglever 34 along passageway 29, the paper forcibly rotates lever 34 in theclockwise direction against resilient force of spring 36 to allowpassage of the paper over lever 34. At the moment, rotation of lever 34is detected by a lever sensor 37 of photosensor. Thus, the paper istransported along passageway 29 from inlet 14 through outlet 20 to astacker 29 attached over validating apparatus 10.

[0007] As shown in FIG. 4, validating sensor 21 and lever sensor 37 areelectrically connected to corresponding input terminals of (inputdevice) CPU 1 whose output terminals (output device) are electricallyconnected to conveyor 16. CPU 1 comprises a one-chip micro-computer ofsuch as large scale integrator (LSI) or discrete circuits to generatecommand outputs from output terminals in response to input signalsreceived by input terminals. Conveyor 16 produces outputs for drivingand controlling convey motor 32. CPU 1 receives from validating sensor21 output signals representing optical or magnetic feature of the paperto compare the output signals from validating sensor 21 with apredetermined optical or magnetic pattern previously stored in a memorylocation 19 in existent memory 12. When output signals from validatingsensor 21 correspond to information stored in memory location 19, CPU 1produces outputs to conveyor 16 which forwards drive signals to conveymotor 32 to transport the paper to outlet 20.

[0008] CPU 1 of validating apparatus 10 shown in FIG. 4, comprises aninput device (not shown) electrically connected to validating sensor 21and lever sensor 37 and an output device (not shown) electricallyconnected to conveyor 16. CPU 1 is electrically connected to existentmemory 12 for storing operational information to produceprogram-controlled command signals from output device of CPU 1 inresponse to input signals received by input device of CPU 1 inaccordance with the operational information stored in existent memory12. Although the embodiment of validating apparatus 10 shows connectionof validating sensor 21 and lever sensor 37 to input device of CPU 1 andconnection of conveyor 16 to output device of CPU 1, variations insetting these elements can be made as necessary. Existent memory 12comprises a memory control device 13 that has memory location 19 forstoring operational program to transport the paper, acquire data fromthe paper and validate the paper, and an information memory 18 forstoring addresses for information stored in memory location 19. CPU 1comprises a control system for computing and controlling which includescontrol terminals for producing retrieval signals to existent memory 12,an inner memory for storing access space, and registers for temporarilyretaining address and information. Address bus of lines A0-A15 isprovided to transmit address signals from CPU 1 to existent memory 12,and a data bus to transmit data from existent memory 12 to CPU 1 so thatCPU 1 designates an address stored in information memory 18 of existentmemory 12 through address bus to read out, through data bus, informationstored in memory location 19 to which addresses are assigned, and then,CPU 1 produces command signals to control conveyor 16 from output deviceof CPU 1 based on the fetched information.

[0009] Operation of CPU 1 and existent memory 12 is describedhereinafter. FIG. 5 is a flow chart showing an operational sequence frominsertion to stacking of the paper. When power switch 38 is turned on inStep 61 to supply electric power from power source 11, a reset signal isgiven to CPU 1 to initialize validating apparatus 10, and at the sametime, CPU 1 forwards a first retrieval signal from RD output terminal toOE input terminal of existent memory 12 which therefore is turned intothe readable mode. Then, CPU 1 accesses information memory 18 throughaddress bus A0-A15 to gain information from memory location 19 to makepreparations for receiving a paper. When the paper is inserted intoinlet 14, inlet sensor 23 detects insertion of the paper in Step 62.When input device of CPU 1 receives a detection signal from inlet sensor23, CPU 1 generates a retrieval signal to OE input terminal of existentmemory 12 from RD output terminal of CPU 1 so that CPU 1 receives fromexistent memory 12 program necessary for conveying paper from inlet 14along passageway 29 in validating apparatus 10, and to provide conveyor16 with command signals from output device of CPU 1. Arriving at Step63, the paper moved by conveyor 16 passes validating sensor 21 whilemagnetic sensor 22 and optical sensors 24 to 26 detect magnetic andoptical features of the moving paper.

[0010] CPU 1 compares detected information from the paper withdenomination information stored in memory location 19 of existent memory12 (in Step 64) to determine correct denomination or kind of the paper(in Step 65). When the correct paper denomination is decided in Step 65,processing moves to Step 66 wherein CPU 1 compares detected informationfrom the paper with information of the genuine document or paperpreviously stored in memory location 19 to validate authenticity of thepaper. When CPU 1 validates and regards the paper as genuine in Step 67,it sends conveyor 16 command signals to drive convey motor 32, transportthe paper along passageway 29 and put the paper in stacker 28 (in Step68). When CPU 1 decides that the denomination of the paper is differentfrom that stored in memory location 19 in Step 65 or when CPU 1determines that the paper is not genuine in Step 67, conveyor 16 isdriven in the adverse direction to return the paper to inlet 14 (Step69).

[0011] By the way, in such a prior art validating apparatus 10, CPU 1must be operated with different program which includes new validatingcriteria when new bills or new valuable papers are issued, and moreover,memory location 19 of existent memory 12 must have validating criteriaprogram for existing and new valuable papers because both of them areput into circulation in markets. In such a case, capacity of memorylocation 19 in existent memory 12 should be enlarged if the existentmemory capacity is too small to install the expanded program. However,expansion of memory capacity would be very difficult because increase ofmemory capacity in existent memory 12 requires increase of the addressnumber and address bus, and therefore, CPU 1 as well as existent memory12 had to be exchanged for new one.

[0012] Accordingly, an object of the present invention is to provide astorage control device of bank structure capable of operating acontrolled system connected to a CPU of smaller capacity in accordancewith information read out from a large capacity storage to CPU. Also,another object of the present invention is to provide a storage controldevice of bank structure which comprises an existent memory exchangeablefor a large capacity storage without exchanging CPU. Still anotherobject of the present invention is to provide an apparatus equipped withsuch a storage control device for validating valuable papers.

SUMMARY OF THE INVENTION

[0013] The storage control device of bank structure according to thepresent invention, comprises a CPU (1) provided with involved input andoutput devices, and a storage (2) connected to CPU (1). Storage (2)comprises a memory control device (3) which has a plurality of bankmemories (9) each for storing information at the memory capacity forprocessing by CPU (1), information addresses (00000h-7FFFFh) assigned toinformation stored in each bank memory and bank addresses(0DF00h-7DF07h) assigned to each bank memory. CPU (1) produces aretrieval signal for switching memory control device (3) to a next bankmemory and timely shifting memory control device (3) into the readablemode so that CPU (1) can read out information from the bank memoryswitched with one of bank addresses (0DF00h-7DF07h) to produce outputsfrom output device of CPU (1) in response to input signals received byinput device of CPU (1) in accordance with information read from thebank memory. Storage (2) detects and temporarily holds one of bankaddresses (0DF00h-7DF07h) for the bank memory to be read out next by CPU(1) when CPU (1) reads the bank memory so that storage (2) supplies theheld bank address to memory control device (3) which thereby is switchedto a next bank memory when CPU (1) produces a next retrieval signal.Accordingly, by switching one of a plurality of bank memories (9) toanother in order, CPU (1) of still small capacity can gain informationfrom switched bank memory for various operation of a controlled systemby CPU (1). Accordingly, control functions can be expanded or altered,still utilizing existing devices without altering CPU (1) of smallcapacity and with exchanging only memory (12) for storage (2).

[0014] CPU (1) produces retrieval signals to fetch information from aselected one of bank memories (9) of memory control device (3) so thatCPU (1) performs predetermined operations in accordance with informationread from selected bank memory, while addressing device (4) detects andtemporarily holds a bank address for bank memory to be accessed next byCPU (1). Then, when CPU (1) produces a next retrieval signal, addressingdevice (4) supplies held bank address to memory control device (3) topositively advance memory control device (3) to a previously designatedand successive bank memory (9) so that CPU (1) can receive predeterminedinformation from memory control device (3).

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] An embodiment of the present invention applied to an apparatus 10for validating valuable papers shown in FIG. 3 is described hereinafterin connection with FIGS. 1 to 3. Same symbols as those shown in FIG. 4are applied to equivalent elements shown in FIG. 1 for omission ofrepeated explanation on the symbolized elements.

[0016]FIG. 1 is a block diagram of an embodiment showing the storagecontrol device of bank structure according to the present invention;

[0017]FIG. 2 is a flow chart showing an operational sequence of anapparatus for validating valuable papers;

[0018]FIG. 3 is a sectional view of an example of the apparatus forvalidating;

[0019]FIG. 4 is a block diagram of a prior art memory device; and

[0020]FIG. 5 is a flow chart showing an operational sequence of a priorart apparatus for validating valuable papers.

BEST MODE FOR CARRYING OUT THE INVENTION

[0021] In the present invention, a large capacity storage 2 can beconnected to CPU 1 in place of existent memory 12 connected to CPU 1. Anembodiment according to the present invention represents an example ofvalidating apparatus 10 shown in FIG. 3 with CPU 1 and storage 2substituted for prior art existent memory 12 connected to CPU 1 shown inFIG. 4. Memory capacity of each bank memory is substantially the same asor greater than memory capacity of existent memory 12 connected to CPU 1before storage 2 is connected to CPU 1, and information stored in afirst bank memory 9 a may contain the same information as at least apart of information stored in existent memory 12, but may contain quitedifferent information from that in existent memory 12. As shown in FIG.4, existent memory 12 comprises address bus of sixteen lines A0-A15 anddata bus of eight lines D0-D7 with memory capacity of 512 kilobits towhich addresses from 00000h-0FFFFh (The symbol “h” indicates ahexadecimal number.) are assigned. Expansion of memory capacity from 512kilobits to 4 megabits requires increase of the address bus number fromcurrent sixteen lines A0-A15 to nineteen lines A0-A18. In thisembodiment, memory capacity can be expanded by substituting storage 2for existent memory 12 from 512 kilobits to 4 megabits eight times.Specifically, as shown in the following Table 1, access space (memorycapacity) can be enlarged from 512 kilobits with address: 00000h-0FFFFhto 4 megabits with address 00000h-7FFFFh by means of additional addressbus of three lines A16-A18 with a first bank memory 9 a of 00000h-0FFFFhto an eighth bank memory of 70000h-7FFFFh. TABLE 1 Information AddressBank Address (Binary Notation) (Hexadecimal Bank Memory A18 A17 A16Notation) 9a First 0 0 0 00000h˜0FFFFh 9b Second 0 0 1 10000h˜1FFFFh 9cThird 0 1 0 20000h˜2FFFFh 9d Fourth 0 1 1 30000h˜3FFFFh 9e Fifth 1 0 040000h˜4FFFFh 9f Sixth 1 0 1 50000h˜5FFFFh 9g Seventh 1 1 060000h˜6FFFFh 9h Eighth 1 1 1 70000h˜7FFFFh

[0022] Incidentally, CPU 1 utilizes only an access space of00000h-0FFFFh with address bus of sixteen lines A0-A15 and data bus ofeight lines D0-D7.

[0023] As shown in FIG. 1, the storage control device of bank structureaccording to the present invention, comprises a CPU 1 and a storage 2connected to CPU 1 available without its any alteration in the formshown in FIG. 4. Storage 2 employs ROM (non-volatile Read Only Memory)or EPROM (non-volatile Electrically Programmable Read Only Memory).Storage 2 comprises a memory control device 3 which has eight bankmemories 9 each for storing information at the memory capacity forprocessing by CPU 1, information addresses 00000h-7FFFFh assigned toinformation stored in bank memories 9 and bank addresses 0DF00h-7DF07hassigned to each of bank memories 9. Storage 2 also comprises anaddressing device 4 connected to CPU 1 and memory control device 3, andaddressing device 4 comprises a latch device 4 a, a synchronizingcircuit 4 b and a resetting device 4 c.

[0024] Latch device 4 a detects and temporarily holds one of bankaddresses 0DF00h-7DF07h for bank memory to be read out next by CPU 1 tosupply the held bank address to memory control device 3 which thereby isswitched to next bank memory when CPU 1 produces a next retrievalsignal. Eight bank memories 9 of memory control device 3 storeinformation to be sent to CPU 1 and bank addresses 0DF00h-7DF07h inhexadecimal notation of bank memory to be read out one after anotherwhen each bank memory is accessed by CPU 1. When CPU 1 produces a nextretrieval signal, latch device 4 a converts bank address stored inhexadecimal notation into binary notation, and then designates a nextbank memory through bank address bus of lines A16-A18 in memory controldevice 3. CPU 1 produces command signals to the controlled system fromoutput device of CPU 1 in accordance with information supplied from oneof bank memories 9 of memory control device 3 in response to inputsignals received by input device of CPU 1.

[0025] A synchronizing circuit 4 b provides latch device 4 a with asynchronizing signal in accordance with a retrieval signal from CPU 1 sothat latch device 4 a furnishes memory control device 3 with one of bankaddresses 0DF00h-7DF07h to designate a next bank memory upon receiving asynchronizing signal from synchronizing circuit 4 b. When memory controldevice 3 is switched to a next bank memory, CPU 1 receives informationfrom the next bank memory switched by forwarding one of informationaddresses 00000h-7FFFFh to memory control device 3 through address busof sixteen lines A0-A15 while latch device 4 a discriminates andtemporarily retains a further next third bank address 0DF00h-7DF07hcontained in previous bank memory.

[0026] Resetting device 4 c comprises a pulse generator such as adifferentiating circuit for generating a reset pulse when power switch38 is turned on to supply electric power to resetting device 4 c frompower source 11. Upon receiving reset pulse from resetting device 4 c,latch device 4 a is designed under programmed control to automaticallyselect therein bank address for designating a first bank memory 9 a tobe first read out from bank memories 9, and forwards to memory controldevice 3 the bank address through bank address bus of lines A16-A18.Delay circuit 7 transmits retrieval signal from RD output terminal 75 ofCPU 1 to OE input terminal 77 of memory control device 3 with time delayto defer shifting of memory control device 3 to the readable mode sothat delay circuit 7 provides a timer which controls timing of latchdevice 4 a for starting receiving and temporarily retaining one of bankaddresses 0DF00h-7DF07h from memory control device 3. CPU 1 performsnecessary operations in accordance with information from first bankmemory 9 a, and produces a retrieval signal from RD output terminal 75when CPU 1 finishes its operations. Retrieval signal from CPU 1 causessynchronizing circuit 4 b to produce a synchronizing signal whichactivates latch device 4 a to convert retained one of bank addresses0DF00h-7DF07h in hexadecimal notation into binary notation which is thenforwarded to bank address bus A16-A18 of memory control device 3 so thatin turn memory control device 3 is switched to and holds a next secondlydesignated bank memory. Accordingly, CPU 1 forwards an informationaddress of 00000h-7FFFFh through address bus A0-A15 to the secondlydesignated bank memory to receive information stored in the secondlydesignated bank memory and carry out operations in accordance with theinformation.

[0027] As bank address of 0DF00h-7DF07h for next one of bank memories 9to be accessed by CPU 1 have been written in preceding one of bankmemories 9 previously accessed by CPU 1, latch device 4 a detects andtemporarily keeps read one of bank addresses 0DF00h-7DF07h written inpreceding one of bank memories 9 when CPU 1 reads content stored in bankmemory. Receiving a synchronizing signal from synchronizing circuit 4 b,latch device 4 a converts retained one of bank addresses 0DF00h-7DF07hfrom hexadecimal to binary notation, and then delivers the bank addressto bank address bus of A16-A18 to switch memory control device 3 to asubsequent bank memory.

[0028] Operation is described hereinafter in connection with the storagecontrol device of bank structure according to the present inventionapplied to validating apparatus 10 shown in FIG. 3.

[0029] In the electric circuit shown in FIG. 2, when power switch 38 isturned on in Step 41 to supply electric power to resetting device 4 cfrom power source, resetting device 4 c produces from the outputterminal a reset signal of high level to a CLR (clear) terminal 71 oflatch device 4 a. Reset signal to CLR terminal 71 of latch device 4 acauses low level voltage at all of data output terminals 1Q-3Q of latchdevice 4 a. At the same time, CPU 1 is reset to produce retrieval signalfrom RD output terminal 75 so that CPU 1 forwards address signal of0DF00h-0DF07h to input terminal IN1 73 of synchronizing circuit 4 b andsimultaneously gives retrieval signal from RD output terminal 75 toinput terminal IN2 74 of synchronizing circuit 4 b. Thereby,synchronizing circuit 4 b generates a clock signal from output terminal76 to furnish CK (clock) terminal 72 of latch device 4 a with leadingrise edge of the clock signal. At this moment, as all data outputterminals 1Q-3Q of latch device 4 a remain in a low level, informationof low level is sent from data output terminals 1Q-3Q to bank addressbus of lines A16-A18 of memory control device 3. Simultaneously, asretrieval signal is applied on OE input terminal 77 of memory controldevice 3 through delay circuit 7 to shift memory control device 3 tofirst bank memory 9 a. Since output signals are kept on data outputterminals 1Q-3Q until a next rising signal is loaded on CK terminal 72of latch device 4 a from synchronizing circuit 4 b, CPU 1 can accessonly address range of 00000h-0FFFFh for first bank memory 9 a denotedimmediately after supply to electric power as shown in Table 1.

[0030] As latch device 4 a of storage 2 receives bank address signals of0DF00h-7DF07h afforded from memory control device 3 to temporarilyretain the bank address, CPU 1 can read out information from unchangedmemory control device 3 within sufficient time interval. In other words,each time banks are switched to a next bank memory, latch device 4 aholds one of bank addresses 0DF00h-7DF07h for the next bank memory towhich CPU 1 can access. Latch device 4 a initially designates a firstbank memory 9 a which stores a protocol for subsequently selecting andassigning any one of third to fifth bank memories 9 c to 9 e.Information stored in first bank memory 9 a is sent from storage 2through data bus D0-D2 of bank memory to CPU 1 which receives andprocesses the information from storage 2 to produce controlled commandsignals from output device of CPU 1 for operating the controlled system.As first bank memory 9 a involves protocol information which indicatesone of bank addresses 0DF00h-7DF07h to designate a successive bankmemory in hexadecimal notation, this bank address for designating thesuccessive bank memory is detected by and temporarily retained throughdata input terminals 1D-3D in latch device 4 a. Receiving clock signalsfrom synchronizing circuit 4 b, latch device 4 a converts into binarynotation any one to be designated next of bank addresses 0DF00h-7DF07hfor third to fifth bank memories 9 c to 9 d in hexadecimal notation sothat latch device 4 a forwards the bank address in binary notation fromdata output terminals 1Q-3Q to bank address bus of A16-A18 in memorycontrol device 3. In other words, unless receiving a clock signal fromsynchronizing circuit 4 b, latch device 4 a never forwards to bankaddress bus of A16-A18 the bank address in binary notation for any oneto subsequently be appointed of third to fifth bank memories 9 c to 9 e.

[0031] Under the circumstances, when a paper is inserted into inlet 14of validating apparatus 10, as shown in FIG. 2, inlet sensor 23 detectsinsertion of the paper (in Step 42) to produce a detection signal to CPU1 which carries out program, and therefore, transports the paper,detects the optical and magnetic features of the paper and validates thepaper in view of information stored in first bank memory 9 a.

[0032] In this case, CPU 1 initially reads information from first bankmemory 9 a to forward to conveyor 16 command signals by protocol storedin first bank memory 9 a so that the paper inserted into inlet 14 istransported along passageway 29 in validating apparatus 10 while CPU 1performs program stored with address ranges 00000h-0FFFFh fordiscriminating denomination of the paper. With movement of processingfrom Step 42 to Step 43, CPU 1 drives convey motor 32 of conveyor 16 totransport the paper along passageway 29 so that magnetic or opticalsensor 22, 24 to 26 of validating sensor 21 detects and deliversmagnetic or optical feature of the paper to CPU 1. Then, CPU 1 comparesdiscerned information from the paper with denomination informationstored in first bank memory 9 a (in Step 44) to decide denomination ofthe paper (in Step 45).

[0033] As shown in FIG. 2, each bank memory stores necessary operationalinformation 00-07 and bank address (protocol) in hexadecimal notation todesignate a next bank memory, and an address of 0DF00h-0DF07h to7DF00h-7DF07h is assigned to each operational information per bankmemory. CPU 1 accesses bank address of 0DF00h-0DF07h to 7DF00h-7DF07hfrom memory control device 3 through address bus A0-A15 and extractsinformation 00-07 to perform the operation under programmed control.

[0034] As shown in FIG. 2, when the paper comes under Category 1 in Step46, processing moves to Step 48 in which memory control device 3 isswitched from first bank memory 9 a to third bank memory 9 c, and thenthe subsequence comes to Step 51. When the paper does not fall underCategory 1 in Step 46, processing moves to Step 47 in which decision ismade on whether the paper comes under Category 2 or not. In Step 47,when CPU 1 decides that the paper corresponds to Category 2, processingmoves to Step 49 in which memory control device 3 is switched from firstbank memory 9 a to fourth bank memory 9 d, and the subsequence comes toStep 51.

[0035] When memory control device 3 is switched from first bank memory 9a to third bank memory 9 c, CPU 1 causes bank addresses 0DF00h-0DF07h toenter into input terminal IN1 73 of synchronizing circuit 4 b, andsimultaneously also supplies input terminal IN2 74 of synchronizingcircuit 4 b with retrieval signal from RD output terminal 75 of CPU 1.Thus, synchronizing circuit 4 b produces a clock signal from outputterminal 76 to give CK terminal 72 of latch device 4 a a leading riseedge of the clock signal so that latch device 4 a converts storedinformation in hexadecimal notation from third bank memory 9 c to besuccessively designated into the information of binary notation which isthen forwarded to memory control device 3 through bank address busA16-A18 because latch device 4 a has already held the informationthrough data input terminals 1D-3D from third bank memory 9 c of memorycontrol device 3. At the same time, retrieval signal is applied to OEinput terminal 77 of memory control device 3 through delay circuit 7,and memory control device 3 is switched from first bank memory 9 a tothird bank memory 9 c so that CPU 1 accesses and reads third bank memory9 c through address bus A0-A15 (in Step 48) to gain information ofaddress 2000h-2FFFFh from memory control device 3 in case the paper isof the denomination already appreciated in Step 45 and belongs toCategory 1 in Step 46, and then the processing comes to Step 51.

[0036] Memory control device 3 ceases the readable mode to stopoutputting information, the instant that CPU 1 terminates the retrievalsignal. Latch device 4 a provides bank address signals in binarynotation for bank address bus A16-A18 of memory control device 3 fromaddress output terminals 1Q-3Q when synchronizing circuit 4 b produces asynchronizing signal to CK terminal 72 of latch device 4 a. If memorycontrol device 3 ceases the readable mode before bank address signalsare provided to bank address bus A16-A18, there would disadvantageouslybe a likelihood of memory control device 3 unable to be switched to anext bank memory although latch device 4 a applies bank address signalfrom data output terminals 1Q-3Q to address bus A16-A18 of memorycontrol device 3. To this end, delay circuit 7 defers timing of aswitching signal supplied from CPU 1 to OE input terminal 77 of memorycontrol device 3 to surely switch memory control device 3 to a next bankafter memory control device 3 receives bank address signal from latchdevice 4 a.

[0037] Third, fourth and fifth bank memories 9 c to 9 e store new oradditional information for a genuine valuable paper or papers. Inaccordance with protocol retained at data output terminals 1Q-3Q, CPU 1can access information stored in third bank memory 9 c with address of20000h-2FFFFh. Third bank memory 9 c stores information 00-07 inhexadecimal notation to which bank address 2DF00h-2DF07h is allocated,and latch device 4 a holds and retains information 00-07 of third bankmemory 9 c which is converted into binary notation when switching thirdbank memory 9 c is switched to a next bank memory.

[0038] In a similar manner for switching memory control device 3 fromfirst bank memory 9 a to third bank memory 9 c, memory control device 3is switched from first bank memory 9 a to fourth bank memory 9 d in Step49 while CPU 1 supplies bank address 0DF00h-0DF07h to input terminal IN173 of synchronizing circuit 4 b, and at the same time furnishesretrieval signal from RD output terminal 75 to input terminal IN2 74 ofsynchronizing circuit 4 b. Thus, synchronizing circuit 4 b againgenerates a clock signal to present a leading rise edge of clock signalto CK terminal 72 of latch device 4 a which retains information 00-07 offourth bank memory 9 d in hexadecimal notation at data input terminals1D-3D for next designation so that latch device 4 a converts information00-07 into information of binary notation and forwards it from dataoutput terminals 1Q-3Q to bank address bus A16-A18 of memory controldevice 3. Simultaneously, retrieval signal is applied to OE inputterminal 77 through delay circuit 7, and memory control device 3 isswitched from first bank memory 9 a to fourth bank memory 9 d which isaccessed by CPU 1 (in Step 49) in case the paper is of the denominationalready appreciated in Step 45 and belongs to Category 2 as shown inFIG. 2. In accordance with protocol retained in data output terminal1Q-3Q, CPU 1 can have access to information stored in fourth bank memory9 d with information address 30000h-3FFFFh. Fourth bank memory 9 dstores information 00-07 with bank address 3DF00h-3DF07h which issupplied to data input terminals 1D-3D of latch device 4 a which retainsinformation 00-07 of fourth bank memory 9 d and utilizes it to switchmemory control device 3 from fourth bank memory 9 d to a next bankmemory. CPU 1 has access to information with information address30000h-3FFFFh of memory control device 3 through address bus A0-A15, andthen processing moves to Step 51.

[0039] When CPU 1 decides that the paper does not come under Category 2in Step 47, memory control device 3 is switched from first bank memory 9a to fifth bank memory 9 e in Step 50. In accordance with a similaroperation to that for switching first bank memory 9 a to third bankmemory 9 c or first bank memory 9 a to fourth bank memory 9 d, memorycontrol device 3 is switched from first bank memory 9 a to fifth bankmemory 9 e so that CPU 1 can have access to fifth bank memory 9 e withinformation address of 40000h-4FFFFh, and simultaneously latch device 4a receives at the data input terminals 1D-3D information 00-07 in fifthbank memory 9 e with bank address 4DF00h-4DF07h. After a bank memory isswitched in accordance with any Category of the paper, CPU 1 performsprogram stored in each bank memory to compare information on the paperoutput from validating sensor 21 with information on genuine paperpreviously stored in third, fourth or fifth bank memory 9 c, 9 d or 9 efor validation of the paper.

[0040] Referring to Step 52, CPU 1 validates authenticity of the paper,and when CPU 1 decides the paper as genuine, it produces a commandsignal to conveyor 16 in Step 53. Accordingly, the paper is conveyed tostacker 28 with rotation of convey motor 32 controlled by conveyor 16,and arranged in stacker 28 secured over validating apparatus 10 (in Step53), and processing moves to Step 54 for resetting bank memories 9. Onthe other hand, when CPU 1 decides in Step 45 that the paper does notcorrespond to denomination stored in first bank memory 9 a or when CPU 1decides in Step 52 that the paper is not genuine, CPU 1 drives conveyor16 in the adverse direction in Step 55 to return the paper to inlet 14,and the process goes to Step 54. In Step 54, bank memory is switched tofirst bank memory 9 a to return operation of validating apparatus 10 toStep 42. As mentioned above, in the embodiment of the present invention,retrieval signal produced by CPU 1 switches memory control device 3 to anext bank memory and simultaneously shifts memory control device 3 tothe readable mode so that CPU 1 reads information from the switched bankmemory with bank address of 0DF00h-7DF07h to generate outputs fromoutput device of CPU 1 to controlled system in accordance withinformation from each bank memory in response to input signals receivedin input device of CPU 1.

[0041] Storage 2 detects and holds one of bank addresses 0DF00h-7DF07hstored in a previous bank memory for a bank memory to be read out nextwhen CPU 1 reads a bank memory, and supplies memory control device 3with the retained bank address to switch memory control device 3 to thenext bank memory, CPU 1 of even small processing capacity can operatethe controlled system in various modes by obtaining information fromplural bank memories 9 switched one after another in a predeterminedorder. Accordingly, without altering an existing CPU 1 of smallprocessing capacity and with exchange of only existent memory 12 forstorage 2, control function can be expanded or altered utilizingexisting devices. In this case, existing CPU 1 can still be used forextremely increased control information by substituting storage 2 forexistent memory 12 connected to CPU 1 because storage 2 may have amemory control device 3 for storing information with the memory capacityseveral times as much as that of existent memory 12.

[0042] The foregoing embodiment of the present invention can be changedin various ways, and the present invention should not be limited to theforegoing embodiment. For example, the storage control device of bankstructure according to the present invention may be applied to anapparatus for validating valuable papers, and would be applicable tomoney handling apparatus for paper currency or coins such as moneycounters, cash registers such as electronic registers, leisureapparatuses such as token dispensers, customer or industrial appliances.The preceding embodiment does not show utilization of second, sixth toeighth bank memories 9 b, 9 f to 9 h for basic operation, however, it isapparent that these memories may store information, judgment criteriaand program for performing operation now shown for reading and executionby CPU 1. In short, the embodiment simply shows an example of bankmemories 9. Bank memories may store bank address to be read out next inbinary notation, not hexadecimal notation so that latch device 4 atemporarily detects and holds the bank address in binary notation. Inthis case, latch device 4 a does not need conversion of notation when itproduces bank address from data output terminals 1Q-3Q to memory controldevice 3. Latch device 4 a receives bank address information throughdata input terminals 1D-3D and retains it in hexadecimal notation forbank memory 9 c to be designated next. If bank address bus A16-A18 hastheir sufficient capacity, bank address information is not convertedinto binary notation, and it can be forwarded in its hexadecimalnotation to bank address bus A16-A18 for designation of a next bankmemory.

Availability in Industry

[0043] The storage control device of bank structure according to thepresent invention utilizes CPU of small capacity for various operationof a controlled system by CPU, and for provision of the device insmaller size. Also, major alterations can be made to operational programof CPU without altering existing CPU of small capacity and withexchanging only memory for storage. For that reason, existing devicescan be successively used without the disposal with expanded or changedcontrol functions for saving of resources and energy. Moreover, thevalidating apparatus according to the present invention can save orreduce cost for improvement of the apparatus when new valuable papersare issued.

1: A storage control device of bank structure comprising a centralprocessing unit with involved input and output devices, and a storageconnected to said central processing unit; said storage comprising amemory control device which has a plurality of bank memories each forstoring information at the memory capacity for processing by saidcentral processing unit, information addresses assigned to informationstored in said bank memories and bank addresses assigned to each of saidbank memories; wherein said central processing unit produces a retrievalsignal for switching said memory control device to a next bank memoryand shifting said memory control device into the readable mode; saidcentral processing unit reads information of the bank memory switchedwith one of bank addresses to produce outputs from the output device ofsaid central processing unit in response to input signals received bythe input device of said central processing unit in accordance with theinformation read from the bank memory; said storage detects andtemporarily holds one of the bank addresses to be read out next by saidcentral processing unit to supply the held bank address to said memorycontrol device which thereby is switched to a next bank memory when saidcentral processing unit produces a next retrieval signal. 2: The storagecontrol device of claim 1, wherein said storage comprises an addressingdevice connected to said central processing unit and memory controldevice for detecting and temporarily holding the bank address of thebank memory to be read out next by said central processing unit tosupply the held bank address to said memory control device which therebyis switched to a next bank memory when said central processing unitproduces a next retrieval signal. 3: The storage control device of claim2, wherein said addressing device comprises a latch device connected tosaid memory control device for detecting and temporarily holding thebank address of the bank memory to be read out next by said centralprocessing unit to supply the held bank address to said memory controldevice which thereby is switched to the next bank memory when saidcentral processing unit produces a next retrieval signal. 4: The storagecontrol device of claim 3, further comprising a synchronizing circuitfor providing said latch device with a synchronizing signal inaccordance with the retrieval signal from said central processing unit,wherein said latch device furnishes said memory control device with bankaddress of the bank memory to be designated next upon receiving thesynchronizing signal from said synchronizing circuit. 5: The storagecontrol device of claim 3 or 4, wherein said central processing unitreceives information from a new bank memory switched through informationaddresses; and said latch device detects and holds a next bank addresscontained in new bank memory. 6: The storage control device of claims 3or 4, further comprising a resetting device for providing said latchdevice with a reset signal when electric power is supplied to saidresetting device; said latch device automatically selects a bank addressfor designating a first bank memory to be first read out of said bankmemories upon receiving the reset signal from said resetting device toforward the bank address to a bank address bus of said memory controldevice when the central processing unit produces the retrieval signal.7: The storage control device of claim 6, wherein memory capacity ofeach bank memory is substantially the same as or larger than that of anexistent memory previously equipped in said storage control device; afirst one of said bank memories stores the same information as at leasta part of information stored in said existent memory. 8: The storagecontrol device of claim 1, wherein said storage can be connected to saidcentral processing unit in lieu of an existent memory previouslyequipped in said storage control device. 9: The storage control deviceof claim 1, further comprising a delay circuit for transmitting theretrieval signal from said central processing unit to said memorycontrol device with time delay to defer switching of the memory controldevice to the readable mode. 10: The storage control device of claim 1,wherein said storage supplies a bank address to bank address bus of saidmemory control device after bank address of bank memory to be designatednext is converted for display when said central processing unit producesa next retrieval signal. 11: A bill-validating apparatus comprising thestorage control device of any one of claims 1, 2, 3, 4, 8, 9 and 10,said bill-validating apparatus further comprising a conveyor fortransporting a bill inserted into an inlet along a passageway; avalidating sensor for detecting optical or magnetic feature of thetransported bill; and a control device for receiving outputs from saidvalidating sensor to compare the received information with previouslystored bill information of bill, validating authenticity and determiningdenomination of the bill, thereby to control said conveyor. 12: Astorage control device of bank structure comprising a central processingunit with involved input and output devices, and a storage connected tosaid central processing unit; said storage comprising a memory controldevice which has a plurality of bank memories each for storinginformation at the memory capacity for processing by said centralprocessing unit, information addresses assigned to information stored insaid bank memories and bank addresses assigned to each of said bankmemories; wherein said central processing unit produces a retrievalsignal for reading information from the bank memories to performoperations in the central processing unit and produce outputs from theoutput devices in response to input signals received by the input devicein accordance with the information from the bank memories; said centralprocessing unit produces a retrieval signal when said central processingunit ceases the operations performed in accordance with the informationfrom the bank memories; said storage comprises an addressing deviceconnected to said central processing unit and memory control device fordetecting and temporarily holding the bank address for the bank memoryto be read out next by said central processing unit to supply the heldbank address to said memory control device which thereby is switched toa next bank memory when said central processing unit produces a nextretrieval signal; said memory control device switched to the next bankmemory is shifted to the readable mode by a retrieval signal from thecentral processing unit which then receives information from theswitched bank memory. 13: The storage control device of claim 12,wherein said addressing device comprises a latch device connected tosaid memory control device for detecting and temporarily holding thebank address of the bank memory to be read out next by said centralprocessing unit to supply the held bank address to said memory controldevice which thereby is switched to the next bank memory when saidcentral processing unit produces a next retrieval signal. 14: Thestorage control device of claim 13, further comprising a synchronizingcircuit connected to said latch device and central processing unit forproviding said latch device with a synchronizing signal in accordancewith the retrieval signal from said central processing unit, whereinsaid latch device furnishes said memory control device with bank addressof the bank memory to be designated next upon receiving thesynchronizing signal from said synchronizing circuit. 15: The storagecontrol device of any one of claims 12 to 14, wherein said storageconverts a bank address for a next bank memory in hexadecimal notationinto the bank address in binary notation, and then supplies theconverted bank address to a bank address bus of the memory controldevice. 16: The storage control device of any one of claims 12 to 14,wherein said latch device discriminates and temporarily retains afurther next bank address contained in a switched new bank memory whenthe memory control device is switched to the next bank memory. 17: Thestorage control device of any one of claims 12 to 14, further comprisinga resetting device for providing said latch device with a reset signalwhen electric power is supplied to said resetting device; said latchdevice automatically selects a bank address for designating a first bankmemory to be first read out of said bank memories upon receiving thereset signal from said resetting device to forward the bank address to abank address bus of said memory control device when the centralprocessing unit produces a retrieval signal. 18: The storage controldevice of any one of claims 12 to 14, further comprising a delay circuitfor transmitting the retrieval signal from said central processing unitto said memory control device with time delay to defer switching of thememory control device to the readable mode. 19: A bill-validatingapparatus comprising: a conveyor for transporting a paper inserted intoan inlet along a passageway; a validating sensor for detecting opticalor magnetic feature of the transported paper; a storage for previouslystoring information of the paper; and a central processing unit forcomparing information of the paper output from said validating sensorwith the information of the paper stored in said storage to validate theauthenticity of denomination of the paper and control a convey motoraccordingly; wherein said storage comprising a memory control devicewhich has a plurality of bank memories each for storing information atthe memory capacity for processing by said central processing unit,information addresses assigned to information stored in said bankmemories and bank addresses assigned to each of said bank memories; saidcentral processing unit performs operations and produces output signalsfrom an output device of the central processing unit in response toinput signals received by an input device of the central processing unitin accordance with the information from the bank memories; said centralprocessing unit produces a retrieval signal to read one of the bankmemories when said central processing unit ceases the operationsperformed in accordance with the information from the bank memories;said storage comprises an addressing device connected to said centralprocessing unit and memory control device for detecting and temporarilyholding the bank address of the bank memory to be read out next by saidcentral processing unit to supply the held bank address to said memorycontrol device which thereby is switched to a next bank memory when saidcentral processing unit produces a next retrieval signal; said memorycontrol device switched to the next bank memory is shifted to thereadable mode by the retrieval signal from the central processing unitwhich then receives information from the switched bank memory to decideon whether the paper comes under Category 1; the central processing unitvalidates the paper by deciding on whether the paper comes underCategory 2 when the paper does not come under the Category 1 to switchthe memory control device to a further next memory bank.